JPS5389334A - Parity forecasting and inspecting current mode arithmetic logic circuit - Google Patents

Parity forecasting and inspecting current mode arithmetic logic circuit

Info

Publication number
JPS5389334A
JPS5389334A JP15868077A JP15868077A JPS5389334A JP S5389334 A JPS5389334 A JP S5389334A JP 15868077 A JP15868077 A JP 15868077A JP 15868077 A JP15868077 A JP 15868077A JP S5389334 A JPS5389334 A JP S5389334A
Authority
JP
Japan
Prior art keywords
forecasting
parity
logic circuit
current mode
arithmetic logic
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP15868077A
Other languages
English (en)
Japanese (ja)
Other versions
JPS618972B2 (en]
Inventor
Waanaa Miraa Hoomaa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Bull HN Information Systems Italia SpA
Original Assignee
Honeywell Information Systems Italia SpA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Honeywell Information Systems Italia SpA filed Critical Honeywell Information Systems Italia SpA
Publication of JPS5389334A publication Critical patent/JPS5389334A/ja
Publication of JPS618972B2 publication Critical patent/JPS618972B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/57—Arithmetic logic units [ALU], i.e. arrangements or devices for performing two or more of the operations covered by groups G06F7/483 – G06F7/556 or for performing logical operations
    • G06F7/575—Basic arithmetic logic units, i.e. devices selectable to perform either addition, subtraction or one of several logical operations, using, at least partially, the same circuitry
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50—Adding; Subtracting
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/38—Indexing scheme relating to groups G06F7/38 - G06F7/575
    • G06F2207/48—Indexing scheme relating to groups G06F7/48 - G06F7/575
    • G06F2207/4802—Special implementations
    • G06F2207/4806—Cascode or current mode logic

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Pure & Applied Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Optimization (AREA)
  • Computing Systems (AREA)
  • Quality & Reliability (AREA)
  • Detection And Correction Of Errors (AREA)
JP15868077A 1977-01-03 1977-12-29 Parity forecasting and inspecting current mode arithmetic logic circuit Granted JPS5389334A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US05/756,457 US4084253A (en) 1977-01-03 1977-01-03 Current mode arithmetic logic circuit with parity prediction and checking

Publications (2)

Publication Number Publication Date
JPS5389334A true JPS5389334A (en) 1978-08-05
JPS618972B2 JPS618972B2 (en]) 1986-03-19

Family

ID=25043573

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15868077A Granted JPS5389334A (en) 1977-01-03 1977-12-29 Parity forecasting and inspecting current mode arithmetic logic circuit

Country Status (2)

Country Link
US (1) US4084253A (en])
JP (1) JPS5389334A (en])

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4163211A (en) * 1978-04-17 1979-07-31 Fujitsu Limited Tree-type combinatorial logic circuit
DE3338742C2 (de) * 1983-10-25 1985-09-05 Siemens AG, 1000 Berlin und 8000 München Schaltungsanordnung zur Prüfbiterzeugung
JPH0224468U (en]) * 1988-07-30 1990-02-19
JP2621480B2 (ja) * 1989-06-06 1997-06-18 日本電気株式会社 加算回路検査装置

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2056229A5 (en]) * 1969-07-31 1971-05-14 Ibm
US3758760A (en) * 1972-04-07 1973-09-11 Honeywell Inf Systems Error detection for arithmetic and logical unit modules
US3925647A (en) * 1974-09-30 1975-12-09 Honeywell Inf Systems Parity predicting and checking logic for carry look-ahead binary adder
US3986015A (en) * 1975-06-23 1976-10-12 International Business Machines Corporation Arithmetic unit for use in a digital data processor and having an improved system for parity check bit generation and error detection

Also Published As

Publication number Publication date
JPS618972B2 (en]) 1986-03-19
US4084253A (en) 1978-04-11

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